1. Field of the Invention
The present invention relates to a high-level synthesis method for generating a circuit description of a digital circuit based on a behavioral description of the digital circuit. In particular, the present invention relates to an allocation method for allocating a resource for executing each process in an operation description to each process.
2. Description of the Related Art
Due to the advancement of techniques for increasing smaller LSI circuits, the number of gates that can be integrated in one chip has increased remarkably. In order to design such a LSI in a short period of time and efficiently, a high-level synthesis technique for generating circuit information based on a behavioral description of hardware has been utilized. An example of the document describing the detail of the high-level synthesis technique includes Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin, “HIGH-LEVEL SYNTHESIS Introduction to Chip and System Design”, Kluwer Academic Publishers, 1992.
FIG. 28 is a flow chart showing a conventional high-level synthesis method. First, in CDFG generation, a CDFG (Control Data Flow Graph) is generated based on an input file describing a behavior of a digital circuit (Step S201). Then, in scheduling, each node of the CDFG representing the contents of processing is allocated to a time synchronized with a dock called Step, based on the generated CDFG and the constraint condition of the digital circuit described in a constraint file, whereby the CDFG is scheduled (Step S202). Next, in allocation and circuit information generation, circuit information and allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling are generated (Step S91). Thereafter, the circuit information is output in outputting (Step S208).
Then, it is determined whether or not the circuit information generated in the allocation and circuit information generation satisfies a predetermined standard representing the constraint condition of the digital circuit (Step S92). When it is determined that the circuit information does not satisfy a predetermined standard (NO in Step S92), the process returns to Step S201.
When it is determined that the circuit information satisfies a predetermined standard (YES in Step S92), the circuit information generated in the allocation and circuit information generation is subjected to logic synthesis processing in logic synthesis (Step S93). Then, it is determined whether or not the circuit information subjected to the logic synthesis processing in the logic synthesis satisfies a predetermined standard representing the constraint condition of the digital circuit (Step S94). When it is determined that the circuit information does not satisfy a predetermined standard (NO in Step S94), the process returns to Step S201.
When it is determined that the circuit information satisfies a predetermined standard (YES in Step S94), the circuit information subjected to the logic synthesis processing in the logic synthesis is subjected to layout processing in layout (Step S95). Then, it is determined whether or not the circuit information subjected to the layout processing in the layout satisfies a predetermined standard representing the constraint condition of the digital circuit (Step S96). When it is determined that the circuit information does not satisfy a predetermined standard (NO in Step S96), the process returns to Step S201. When it is determined that the circuit information satisfies a predetermined standard (YES in Step S96), the process is completed.
Thus, in a design flow of a LSI starting from the high-level synthesis, the design proceeds in the following order: high-level synthesis, logic synthesis, and layout, using a behavioral description of hardware as an input. If the design constraint is not satisfied in each operation, the process is restarted from the high-level synthesis in the worst case.
Conventionally, in order to minimize a manual return loss from a downstream operation after the high-level synthesis, in the high-level synthesis, the maximum shared number of arithmetic operation unit resources and memory resources is limited, and the connection number between the arithmetic operation unit resources and the memory resources is limited so as to prevent the wiring from being congested during layout (“High-level synthesis considering a wiring resource”, Nishio, Kaneko, Tayu, in “Technical Report of IEICE, VLD98-147, pp.49-56, 1999-03).
Furthermore, in the layout, arrangement is performed so that the connecting line between the resources having an effect on circuit performance is not too long, or the congestion degree in a layout region is not high. Thus, measures are taken separately in the respective operations, whereby manual return is minimized.
However, the above-mentioned measures have been taken by human beings from an experimental point of view. Therefore, the high-level synthesis and the layout are not coordinated. Furthermore, in the development of a LSI, several months are required for completing the operations from the high-level synthesis to the layout. Therefore, when a manual return loss of returning from a downstream operation to an upstream operation occurs, a LSI cannot be put on the market at an early time.
According to the conventional high-level synthesis method, a circuit is produced only based on the design constraint created by the experimental determination of human beings without analyzing problems arising in downstream operations (in particular, problems arising in the layout) in detail. This makes it necessary to provide a use limit for a circuit adopting a high-level synthesis system, such as a circuit in which a design constraint regarding the performance, area, and the like is not critical, a circuit having a margin of a development time, or a circuit with a small scale, which can be manually corrected by a human being in a downstream operation.
Furthermore, in the case where a design constraint is not satisfied in a downstream operation after a high-level synthesis operation, in order to reflect feedback information from the downstream operation to a high-level synthesis method, a program file and a design constraint file to be input to a high-level synthesis system need to be corrected.